Process design involves understanding the interaction between every possible element that leads to selection of an imprint process. They distill down
to a few clear limiting cases, and several intermediate cases.

The limiting cases are :

Integrated circuits – requires pattern transfer, fine overlay, low defects, high throughput, on complex device structures. Leads to a S&R, low pressure,
low viscosity, room temperature, UV cure process with a hard surface mold, using  planarization processes  over the device structures.

Blue ray optical disks – requires single layer, surface patterning of a thick polymer layer, with limited align and matched X and Y distortion, and
external error correction. Leads to high pressure, thermal imprint process.

The following is a generic analysis of some of the key factors. This gets very complex, for more detail
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Initial state        
The substrate surface flatness and the presence of device structures directly effects residual layer variation and line width control during etch. As a
result it drives the choice of conformality solution and planarization in the imprint process.

Incoming wafer cleanliness is essential to a successful imprint.

Final state
Resist or Functional
If the final state is a patterned device layer, the imprint material must be compatible with the pattern transfer etch. If the imprint material remains in the
final state as a functional material, then the imprint material must be compatible with the final application. This adds a large number of additional
constraints to the imprint materials, and the selection of imprint process.

Pattern type
The regularity of the pattern has an impact on pattern generation, and on the residual layer variation that results from the difficulty of moving imprint
fluid around with thin residual layers. Holes or bridges force the use of functional materials.

Chemical uniformity
Surfaces with non uniform chemical characteristics are by implication functional materials, a low viscosity drop system can be used, or transfer
printing with a ink pattern otherwise known as micro contact printing.

Process
Field size
The field to be as large as possible based on constraints; it must be a multiple of the device size, so large devices require large fields, the mold and
substrate must be separated after imprint which is more difficult as  the field gets larger. In integrated device applications, the mold must be defect
free, which limits the field size.  Finally the overlay relative to the field size has a major impact of on the complexity of the system design

Line width control
The line width control depends  on the mold, and the control of the etch process through the residual layer and any planarization layers. As such, it is
strongly affected by  incoming wafer flatness  and device structures.

Align and overlay / field size.
The overlay requirement relative to the field size in parts per million can be compared to the thermal expansion coefficient of the components. For
instance +- 25 nm overlay on a 25 mm field is 1 ppm of error. The expansion coefficient of silicon is 10 ppm per C, and fused silica is 1 ppm per C so
thermal control of at significantly less than  0.1 C is required. This forces a S&R, room temperature UV cure imprint solution. Given that wafers are
processed with 10’s of ppm of magnification change due to thermal processing, it also forces the need for magnification correction.

Defects and process life
The defects sensitivity of different applications varies widely, from 30 layer integrated circuit where every layer must be perfect, to a optical grating which
has inherent redundancy. The defect sensitivity has an extreme effect on all elements of the system and process. For instance a hard surface mold is
essential to maintaining low defect density. Incoming wafer cleanliness is also essential.

Imprinting technique
The imprinting technique is controlled by the properties of the final imprint material, and the types of precursors that are available. In the case of
resists, a low Tg final material can be produced from crosslinked monomer mixtures as precursors. In the case of functional materials, a high Tg final
material may be formed by thermal imprinting a low molecular weight, low Tg precursor, followed by a “curing” step after imprint to create the final
material.

Throughput
Throughput is inversely proportional to the (substrate size / field size) squared  or the  number of steps. Each step involves a mold, set and separation  
times. The longest time is typically the mold time as it requires the displacement of liquid through a residual layer gap that is typically a fraction of the
feature size.

Mold
The mold compliance and surface hardness are driven by the substrate flatness and defect density requirements. For UV imprinting on a opaque
substrate, the patterned area of the mold must be transparent. In addition for S&R imprint on a spin on layer, the unpatterned area must be opaque.
Line width control, defect density and positioning of the features on the mold are all critical.

Cost Of Ownership (COO)
The COO of imprint in $ per substrate is a function of 3 major components;

1)        Total cost of all tools/ throughput
2)        Mold cost / mold life
3)        Consumables per substrate

It is very important to do an apples to apples comparison of all process operations between initial and final states. It is also important to indentify the
costs of automation levels at each step so that the real productive throughput can be achieved.

The mold life and cost can be highly variable, in fact one strategy is to make the mold itself a short life, low cost, consumable by making low cost
replicas.

The consumables per substrate are affected by the raw material cost and the deposition technique, so drop on demand or direct sheet coating
techniques can sharply reduce the volume of imprint material.

Total COO per layer for a 45 nm node IC  is targeted at $50 - $300, of which system ($30M) depreciation over 3 years is $10. The largest component is
the contribution of mask cost over the total number of wafers processed. The total number of wafers will be determined by the mask life or wafer deand
whichever is smallest. The demand is often surprisingly small.

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Process Design